TransEDA produce code coverage tools for simulators using High Level Definition Languages (HDLs) to simulate silicon designs. These measure the percentage of an HDL model excercised by a testbench during a simulation highlighting the untested parts of the model carrying the biggest risk of defects. This enables you to save time, optimise the simulation and improive the quality of your model.
CoverPlus is a regression test optimisation tool. It allows users to compare the relative coverage of all testcases within a test case suite. This allows users to identify those tests that are critical and those that add less to the test. This allows tests to be run in the right order allowing errors to be found more quickly.
TransEDA have developed a complex and powerful analysis library written in C++. Tessella added a graphical user interface to this to allow users to easily view the results, order the tests and view and analyse the code of the test. Easy of use facilities such as drag and drop, mouse column resizing and user colour selection have beed added.
An example window is shown below:
This GUI was written using C++ and Motif and runs on a variety of Unix platforms (Sun, RS6000, HP). To minimise costs, various shareware packages were used that proved high quality and flexible. Costs were also kept down further by re-using some utility Motif classes from Tessella's other Motif projects.
TransEDA were enhancing their processing classes at the same time as Tessella were developing the GUI. This demanded a close and flexible working relationship to ensure smooth progress.